In the delivery of computer processing power to customers or end users, it is sometimes desirable to offer a processing unit with a controlled level of performance that is less than the highest level of performance that could be achieved. For example, in the mainframe computing industry, the price charged for a processing unit is often directly related to performance, and so reducing the maximum allowable performance of a delivered unit allows the manufacturer to deliver a product at a controlled level of performance and to charge the customer a lower price than would be offered for a unit that would deliver maximum performance. This practice is common and fully accepted in the computer industry.
In a complex computer system, achieving accurate degradation of performance in a precisely controlled manner to obtain a certifiable submodel rating is a not trivial task. The problem is made complex by many factors.
Some examples of these factors are:
                1) Instructions in a processor, whether implemented in hardware or in a software emulation, may not require the same amount of time for execution.        2) In a software emulation, or in the firmware to control a hardware based central processing unit, instructions used to control and perform the emulation of a processor may themselves not execute in the same amount of time each time they are executed.        3) The same series of instructions, when executed multiple times, may vary, sometimes widely, in the amount of time required to complete either single instructions or a series of instructions. This can be caused either by direct factors such as cache miss or by indirect causes such as bus interference from other programs running on another processor.        4) In offering a submodel, it is desirable to both the customer and the manufacturer that the degradation of performance appear to the end user as being smoothly applied across all elements of a program, not appearing as though one element performs at a high speed and another unit at a degraded, compensating, low speed.        5) The degradation of a processor should allow for achievement of a wide range of degradation without changes in the basic procedure or complex measurements to achieve the selected level of degradation.        6) The time required to sample an interval of time in a processor performing an emulation does not in itself take zero time, so this is a subtle factor in both choosing and implementing the procedure for degradation.        
Embodiments of the present invention address and resolve these considerations.